Gated-Demultiplexer Tree Buffer for Low Power Using Clock Tree Based Gated Driver

With the progress of VLSI technology, delay buffer plays an important role affecting the circuit design and performance. This paper presents the design of low power buffer using clock gating and gated driver tree. Since delay buffers are accessed sequentially, it adopts a gated clock ring counter addressing scheme. The ring counter employs double edge triggered (DET) flip flops instead of traditional flip flop to half the operating frequency. Also for generating clock gating signals, combinational elements (C-element) are implemented in the control logic to avoid the increasing loading of the global clock signal. For the clock distribution network, a gated driver tree technique is used and it further reduces the power consumption. In addition, this technique is used in the input and output ports of the memory to decrease their loading. The proposed delay buffer consumes less power comparing to the conventional delay buffers.